1 single event and total dose hardened, high-speed, dual output pwms is-1825asrh, is-1825bsrh, is-1825bseh, ISL71823ASRH, isl71823bsrh the single event and total dose hardened pulse width modulators are designed to be used in high frequency, switching power supplies in either voltage or current-mode configurations. these designs include a precision voltage reference, a low power start-up circuit, a high frequency oscillator, a wide-band error amp lifier and a fast current-limit comparator. the is-1825asrh, is-1825bsr h and is-1825bseh feature dual, alternating output operatin g from zero to less than 50% duty-cycle, while the ISL71823ASRH and isl71823bsrh features dual, in-phase output op erating from zero to less than 100% duty cycle. the ?b? versions test the delay from clock out to pwm output switching after power has been applied to the modulator (t pwm ) (see figure 3). the isl-825bseh is wafer-by-wafer acceptance tested to 50krad(si) at a low dose rate of 10mrad(si)/s. constructed with the intersil rad-hard silicon gate (rsg) dielectrically isolated bicmos process, these devices are immune to single event latch-up and have been specifically designed to provide a high level of immunity to single event transients. all specified paramete rs are guaranteed and tested for 300krad(si) total dose performance. related literature ? is-1825asrh radiation test report ? is-1825asrh single event effects report features ? electrically screened to dla smd# 5962-02511 ? qml qualified per mil-prf-38535 requirements ? eh version is wafer-by-wafer acceptance tested to 50krad(si) (ldr) ?radiation environment - high dose rate (50-300rad(si)/s). . . . . . . . . . . 300krad(si) - low dose rate (0.01rad(si)/s) . . . . . . . . . . . . . . .50krad(si) - latch-up immune. . . . . . . . . . . . . . . . dielectrically isolated - seu immune . . . . . . . . . . . . . let = 35mev/mg/cm 2 (max) ? oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . 1mhz (max) ? high output drive current . . . . . . . . . . . . . . . . . . 1a peak (typ) ? low start-up current. . . . . . . . . . . . . . . . . . . . . . . 300a (max) ? undervoltage lockout - start threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8v (max) - stop threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6v (min) - hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mv (min) ? pulse-by-pulse current limiting ? programmable lead ing edge blanking applications ? voltage or current-mode switching power supplies ? control of high current mosfet drivers ? motor speed and direction control pin configurations is1-1825asrh, is1-1825bsrh, is-1825bseh isl71823bsrhvd, ISL71823ASRHqd (cdip2-t16 sbdip) top view is9-1825asrh, is9-1825bsrh, is9-1825bseh ISL71823ASRHqf, isl71823bsrhvf (cdfp4-f20 flatpack) top view 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 inv non-inv e/a out clk/leb rt ct ss ramp vref out b vc pgnd out a gnd ilim/sd vcc 2 3 4 5 6 7 8 120 19 18 17 16 15 14 13 nc inv non-inv e/a out clk/leb rt ct ramp 9 10 12 11 ss nc vref vcc out b pgnd vc vc pgnd out a gnd ilim/sd may 23, 2013 fn9065.5 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2012, 2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
is-1825asrh, is-1825bsrh, is-1825 bseh, ISL71823ASRH, isl71823bsrh 2 may 23, 2013 fn9065.5 ordering information ordering/smd numbers (note 1) part number (notes 2, 3) temperature range (c) package (pb-free) pkg. dwg. # is0-1825asrh/sample is0-1825asrh/sample -50 to +125 5962f0251101v9a is0-1825asrh-q -50 to +125 die 5962f0251101qec is1-1825asrh-8 -50 to +125 16 ld sbdip d16.3 5962f0251101qxc is9-1825asrh-8 -50 to +125 20 ld flatpack k20.a 5962f0251101vec is1-1825asrh-q -50 to +125 16 ld sbdip d16.3 5962f0251101vxc is9-1825asrh-q -50 to +125 20 ld flatpack k20.a is1-1825asrh/proto is1-1825asrh/proto -50 to +125 16 ld sbdip d16.3 is9-1825asrh/proto is9-1825asrh/proto -50 to +125 20 ld flatpack k20.a 5962f0251102qec ISL71823ASRHqd -50 to +125 16 ld sbdip d16.3 5962f0251102qxc ISL71823ASRHqf -50 to +125 20 ld flatpack k20.a 5962f0251102vec ISL71823ASRHvd -50 to +125 16 ld sbdip d16.3 5962f0251102vxc ISL71823ASRHvf -50 to +125 20 ld flatpack k20.a 5962f0251102v9a ISL71823ASRHvx -50 to +125 die ISL71823ASRHd/proto ISL71823ASRHd/proto -50 to +125 16 ld sbdip d16.3 ISL71823ASRHf/proto ISL71823ASRHf/proto -50 to +125 20 ld flatpack k20.a ISL71823ASRHx/sample ISL71823ASRHx/sample -50 to +125 die 5962f0251103v9a is0-1825bsrh-q -50 to +125 die 5962f0251103qec is1-1825bsrh-8 -50 to +125 16 ld sbdip d16.3 5962f0251103qxc is9-1825bsrh-8 -50 to +125 20 ld flatpack k20.a 5962f0251103vec is1-1825bsrh-q -50 to +125 16 ld sbdip d16.3 5962f0251103vxc is9-1825bsrh-q -50 to +125 20 ld flatpack k20.a 5962f0251104qec isl71823bsrhqd -50 to +125 16 ld sbdip d16.3 5962f0251104qxc isl71823bsrhqf -50 to +125 20 ld flatpack k20.a 5962f0251104vec isl71823bsrhvd -50 to +125 16 ld sbdip d16.3 5962f0251104vxc isl71823bsrhvf -50 to +125 20 ld flatpack k20.a 5962f0251104v9a isl71823bsrhvx -50 to +125 die 5962f0251105v9a is0-1825bseh-q -50 to +125 die 5962f0251105vec is1-1825bseh-q -50 to +125 16 ld sbdip d16.3 5962f0251105vxc is9-1825bseh-q -50 to +125 20 ld flatpack k20.a 5962f1222801vxc isl70417sehvf -55 to +125 14 ld flatpack k14.a notes: 1. specifications for rad hard qml devices are controlled by the defense logistics agency land an d maritime (dla). the smd numbe rs listed in the ?ordering information? table must be used when ordering. 2. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. 3. for moisture sensitivity level (msl), please see device information page for is-1825asrh, is-1825bsrh is-1825bseh ISL71823ASRH isl71823bsrh . for more information on msl please see tech brief tb363 .
is-1825asrh, is-1825bsrh, is-1825 bseh, ISL71823ASRH, isl71823bsrh 3 may 23, 2013 fn9065.5 typical performance curves figure 1. oscillator frequency vs r t and c t figure 2. maximum duty cycle vs r t 1 10 100 r t timing resistance (k ) frequency (khz) c220pf c470pf c1000pf c2200pf c4700pf c22nf c10nf 10 100 1k 10k 110100 50 60 70 80 90 100 d max (%) r t timing resistance (k ) d max timing diagram figure 3. t pwm delay timing diagram v cc , v c clk out a/b 12v t pwm 0v 0v 0v
is-1825asrh, is-1825bsrh, is-1825 bseh, ISL71823ASRH, isl71823bsrh 4 may 23, 2013 fn9065.5 die characteristics die dimensions 4310m x 5840m (170 mils x 230 mils) thickness: 483m 25.4m (19 mils 1 mil) interface materials glassivation type: phosphorus silicon glass (psg) thickness: 8.0ka 1.0ka top metallization type: alcu (99.5%/0.5%) thickness: 16.0ka 2ka backside finish silicon process radiation hardened silicon gate, dielectric isolation assembly related information substrate potential unbiased (di) additional information worst case current density < 2 x 10 5 a/cm 2 transistor count: 585 metallization mask layout vc vc vref inv non-inv e/a out clk/leb ct ramp ss ilim/sd ognd gnd out a pgnd pgnd out b vcc notes: 1. both the ognd (oscillator ground) and the gnd (con trol circuit ground) pads must be bonded to ground. these pads are both bonded to the gnd pin on the packaged devices. 2. all double-sized bond pads must be double bonded for current sharing purposes. rt rt
is-1825asrh, is-1825bsrh, is-1825bseh, ISL71823ASRH, 5 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com may 23, 2013 fn9065.5 for additional products, see www.intersil.com/en/products.html about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the largest markets within th e industrial and infr astructure, personal computing and high-end consumer markets. for more information about intersil, visit our website at www.intersil.com . for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions fo r improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html . reliability reports are also available from our website at http://www.intersil.com/en/support/q ualandreliability.html#reliability revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change april 23, 2013 fn9065.5 removed part number is-1825aseh and added part numbers is-1825bseh, is-1825bsrh, and isl71823bsrh to ordering information table on page page 2. smd numbers in ordering information table corrected. added timing diagram for clk to out delay t pwm april 5, 2012 fn9065.4 updated to new intersil template added part is-1825aseh to title and ordering information changed dscc to dla. september 25, 2008 fn9065.4 added typical oscillator performance curv es. updated ordering information by adding pkg and pkg dwg number and also added sample parts. february 19, 2008 fn9065.3 added ISL71823ASRH wh ich is a metal option of the is-1825asrh. june 14, 2005 fn9065.2 cosmetic edit only. changed "u" to "" on pg 1 features added ISL71823ASRH which is a metal option of the is-1825asrh. june 14, 2005 fn9065.1 removed "trimmed oscillat or discharge current" from the features section of both datasheets since the oscillator is not trimmed. cosmetic edit only. changed "u" to "" on pg 1 features june 21, 2002 fn9065.0 initial release
is-1825asrh, is-1825bsrh, is-1825 bseh, ISL71823ASRH, isl71823bsrh 6 may 23, 2013 fn9065.5 package outline drawing ceramic metal seal flat pack packages (flatpack) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. this dimension allows for off- center lid, meniscus, and glass overrun. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and fini sh thickness. the maximum lim- its of lead dimensions b and c or m shall be measured at the cen- troid of the finished lead surfaces , when solder dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k20.a mil-std-1835 cdfp4-f20 (f -9a, configuration b) 20 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.540 - 13.72 3 e 0.245 0.300 6.22 7.62 - e1 -0.330-8.38 3 e2 0.130 - 3.30 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.00 - 0.00 - 6 m - 0.0015 - 0.04 - n20 20- rev. 0 5/18/94
is-1825asrh, is-1825bsrh, is-1825 bseh, ISL71823ASRH, isl71823bsrh 7 may 23, 2013 fn9065.5 package outline drawing ceramic dual-in-line me tal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this conf iguration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d16.3 mil-std-1835 cdip2-t16 (d-2, configuration c) 16 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.840 - 21.34 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n16 168 rev. 0 4/94
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